- Detailed information on America’s most popular National Parks, including key features, history, maps, campgrounds, hiking trails, current weather and alerts. The application is aimed to help Tourists and Hikers plan their visit.
- Designed with MVVM architecture, Repository Pattern for modularization and testability.
- Implemented Multi-threading/asynchronous operations using RxJava Schedulers to improve app performance.
- Integrated RESTful API to get park, trail and weather data using Retrofit - RxJava.
- Refactored entire app to use Android Jetpack - LiveData, ViewModel, and Room to improve data consistency.
- Implemented SQLite database using Room - RxJava for Offline mode access.
- Implemented push notification, banner ads and shared preferences to improve user experience.
- Designed UI for multiple phone and tablet sizes with Accessibility support to increase adoption across multiple devices.
- Implemented Expresso and JUnit tests for UI testing to improve app quality.
- Designed and implemented Home Screen Widget for easy user access.

- Uses the Design Support library and its provided widget types (FloatingActionButton, AppBarLayout, SnackBar, etc).
- Uses CoordinatorLayout for the main Activity.
- Theme extends from AppCompat.
- Provides a Floating Action Button for the most common action(s).
- Properly specifies elevations for * bars, FABs, and other elements specified in the Material Design pecification.
- Has a consistent color theme defined in styles.xml. Color theme does not impact usability of the app.
- Provides sufficient space between text and surrounding elements.
- Uses images that are high quality, specific, and full bleed.
- Uses fonts that are either the Android defaults, are complementary, and aren't otherwise distracting.

- Uses Exoplayer to show recipe step videos.
- Mark Favorite to display Widget on home screen.
- Supports UI for Mutiple Phone and Tablet sizes.
- Uses Expresso Unit tests for UI and Intents.

- Browse Popular and Top-Rates movies.
- Watch trailers and read reviews.
- Mark Favorites for future viewing.
- Supports UI for Mutiple Phone and Tablet sizes.
- Offline Viewing mode.
- Automatic Daily update.

- Browse Popular and Top-Rates movies.
- Watch trailers and read reviews.
- Mark Favorites for future viewing.
- Supports UI for Mutiple Phone and Tablet sizes.
- Offline Viewing mode.
- Automatic Daily update.

Each turn:
- The player flips one card over to reveal its underlying symbol.
- The player then turns over a second card, trying to find the corresponding card with the same symbol.
- If the cards match, both cards stay flipped over.
- If the cards do not match, both cards are flipped face down.
- The game ends once all cards have been correctly matched.

- 5+ years of industry experience in ASIC Design Verification and EDA Software applications engineering.
- Developed custom solutions with SystemVerilog HDL using Object-Oriented programming (OOP) to drive product adoption across a diverse set of customers.
- Implemented ground-up Functional Verification flows, methodologies and tool automation for increase in regression throughput by 30%.
- Optimized simulation runs to minimize memory footprint by 60%, and increase compile-run time performance by 40%.
- Extensively collaborated with cross functional product engineering and sales teams leading to a 2M+ annual revenue growth.

- Troubleshoot and resolved customer’s technical problems to increase their productivity with Questa Sim, 0in/Questa CDC and Formal.
- Developed technical training and content for new features and product updates.
- Participated in pre and post sales engagements, performed competitive customer evaluations, offered custom implementations, and made several customer presentations.
- Furthered efforts to increase usage of CDC at Mentor Graphics’ strategic customer site, leading to a 1M+ revenue gain.
- Developed strong technical relationships with the customers, sales teams, and the product engineering teams.
- Communicated customer’s technical requirements along with priority and impact, influencing the product team to meet customer's needs and helped shape product direction. - Mentored colleagues and new hires.
- Focus Areas: HDL, Verification, OVM/UVM, Coverage, Performance Optimization, Clock Domain Crossing Analysis and Formal Verification.

Highlights:

- Performed SystemVerilog-UVM migration for the front-end verification team at key customer site.
- Deployed and Integrated Mentor’s Verification IP with customer’s verification environment.
- Developed testbench architecture using UVM modularizing the testbench into different subunits.
- Developing the UVM drivers for the different type of inputs driven into the design.
- Qualified test runs by developing monitors for functional coverage which in turn was connected to the scoreboard for packet comparison.
- Analyzed and debug functional failures in customer’s design to determine if it is a design or test bench issue.
- Developed PERL scripts and Makefiles to setup unified run flow with error reporting for debug, regression and coverage.
- Optimized simulation runs to minimize memory footprint and increase performance in key areas of regression and coverage.
- Developed interface coverage for SOC sub-system using functional coverage models.
- Enhanced coverage driven testplans to capture maximum functional coverage using test-ranking and refined cross coverage.
- Assisted in integrating Mentor Verification IPs (VIP) into existing customer’s Verification environment.

- Involved in development of constrained random verification (CRV) environment using UVM that generated random transactions for HDD Read Channel Interleaver block at block level and system level.
- Updated verification plan and implemented test cases to finish the outstanding verification of a block in the architecture.

- Debugged bench testing of engineering ASIC samples for hardware design characterization using off the shelf test equipment.
- Involved on development in automated data collection and bench setups using Perl scripting language.

- Constrained Random TB development and test implementation for Ingress/Egress pipeline stages of Ethernet network switching chips.
- Ran regressions, analyzed results and updated verification status based on test results. Reviewed the testplan from previous generation product and validate with latest product testplan. Developed Perl scripts to automate RTL simulation and result capture for report generation.